(1) Field of the Invention
The invention relates to the general field of thin film transistors, more particularly to the formation of the source-drain gap by a self-alignment method.
(2) Description of the Prior Art
Thin film transistors (TFTs) have come into widespread use in, among other applications, liquid crystal displays. Most commonly they are fabricated by first laying down a gate electrode on an insulating substrate, then a layer of gate insulation, then a layer of undoped amorphous silicon and then a heavily doped layer of silicon (usually N+) over the preceding silicon layer.
Parasitic capacitances can appear in such a structure in unpredictable ways because of misalignment between source and drain. Additional tolerances must be allowed in the mask design to avoid possible non-contact problems and this can also introduce undesired parasitic capacitances.
An example of a TFT structure, typical of the prior art, is shown in schematic cross-section in FIG. 1. Gate electrode 2 has been formed on one surface of insulating substrate I and then overcoated with gate insulation layer 3 followed by amorphous silicon layer 21 and heavily doped (N+ or P+) layer of amorphous silicon 22. Layers 21 and 22 were then photolithographically shaped to the outside dimensions seen in FIG. 1, following which metal layer 24 was deposited over the structure. Conventional photolithography was then again used to partially remove layers 24 and 22 to form gap 25.
In addition to the misalignment and excess overlap problems already discussed, this method has the additional disadvantage that, if underetching occurs during the removal of layer 22, when gap 25 is forming, a certain amount of N+ layer 22 will be left on the surface of amorphous silicon layer 21, shorting it out, while, if overetching occurs, the thickness of layer 21 will be less than intended and performance of the device will be degraded.
The over/under etching problem has been partly solved in the prior art by the addition of an etch stop layer such as layer 23 in FIG. 2 typically comprising silicon nitride. This adds several steps to the process, notably the deposition and shaping of 23. Additionally, as shown, 23 does not fully cover amorphous silicon layer 21. Consequently, during the shaping of 23, the uncovered surfaces of 21 will be damaged by the plasma that is used to etch 23. This leads to an increase in the contact resistance between 21 and the N+ contacting layer 22.
In reviewing the prior art we have found that Fukami et al. (U.S. Pat. No. 5,103,330 Apr. 7 1992), Noguchi (U.S. Pat. No. 5,289,016 Feb. 22 1994), and Shannon (U.S. Pat. No. 5,130,829 Jul. 14, 1992) all describe thin film transistors, but none of these is self-aligned. Kobayashi et al. (U.S. Pat. No. 5,414,278 May 9, 1995) do describe a self-aligned structure but it is quite different from that of the present invention, being a thin film analog of the salicide (self-aligned silicide) structure, which the present invention is not. In the Kobayashi structure, both gate electrode and gate insulation act together as the self-alignment mask during the formation of the source and drain regions by means of ion implantation. We also note that the Kobayashi structure comprises polycrystalline silicon for the channel region.
Several other self-aligning structures and methods were also found. These include Takeda et al. (U.S. Pat. Nos. 4,958,205 Sep. 1990 and 5,137,841 Aug. 1992), Diem (U.S. Pat. No. 4,715,930 Dec. 1987), Szydlo et al. (U.S. Pat. No. 4,685,195 Aug. 1987), and Chenevas-Paule et al. (U.S. Pat. No. 4,587,720 May 1986). All of these inventions, while exposing photoresist by means of radiation that has been passed through the substrate, depend on the use of so-called positive photoresists (exposed portion is removed during development), either alone or in conjunction with additional steps using negative resists. Positive resists react to light in the visible portion of the spectrum. This makes them less convenient to use than negative photoresists that are sensitive to ultraviolet light. Additionally, as device dimensions shrink, processes that depend on visible light will run into resolution problems sooner than those using the shorter ultraviolet wavelengths.